In the current epoch with fast scientific and technological development, Liquid Crystal Displays have been widely used in electronic display products such as televisions, computers, telephones and personal digital assistants. A Liquid Crystal Display includes a source driver, a gate driver and a Liquid Crystal Display panel. A pixel array is provided in the Liquid Crystal Display panel, and the gate driver is used to turn on the corresponding pixel rows in the pixel array sequentially, to transfer pixel data outputted from the source driver to pixels so as to display an image to be displayed.
Shift registers are generally used as gate drivers for sequentially turning on the corresponding pixel rows in the pixel array in the prior art. Referring to FIGS. 1 and 2, a schematic diagram showing the structure of the existing shift register is shown in FIG. 1, and an operation timing diagram of the shift register shown in FIG. 1 is shown in FIG. 2.
As shown in FIG. 1, a conventional shift register includes: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6, where, a gate of the first transistor M1 is connected to a first clock signal terminal CK, a source of the first transistor M1 is connected to an input terminal IN of the shift register, and a drain of the first transistor M1 is connected to a gate of the second transistor M2; a drain of the second transistor M2 is connected to a first level signal terminal, and a source of the second transistor M2 is connected to a drain of the fourth transistor M4; a gate of the third transistor M3 is connected to the first clock signal terminal CK, a source of the third transistor M3 is connected to a second level signal terminal, and a drain of the third transistor M3 is connected to a source of the fourth transistor M4; a gate of the fourth transistor M4 is connected to a second clock signal terminal CKB; a gate of the fifth transistor M5 is connected to the drain of the third transistor M3 and the source of the fourth transistor M4, a drain of the fifth transistor M5 is connected to the first level signal terminal, a source of the fifth transistor M5 is connected to an output terminal OUT of the shift register, and a first capacitor C1 is connected between the gate and the drain of the fifth transistor M5; a gate of the sixth transistor M6 is connected to the drain of the first transistor M1, a source of the sixth transistor M6 is connected to the second clock signal terminal CKB, a drain of the sixth transistor M6 is connected to the output terminal OUT of the shift register, and a second capacitor C2 is connected between the gate and the drain of the sixth transistor M6.
Each of the first to sixth transistors M1-M6 is a P-channel Metal Oxide Semiconductor (PMOS) transistor. Herein referring to FIG. 2, an operation timing of the shift register is described as following: a high level signal VGH is provided from the first level signal terminal, a low level signal VGL is provided from the second level signal terminal, an input signal in received from the input terminal of the shift register is a low level pulse signal, a first clock signal ck is received from the first clock signal terminal, and a second clock signal ckb is received from the second clock signal terminal, wherein the second clock signal ckb has a phase inverse to a phase of the first clock signal ck. With the above operation timing, the input signal in is shifted and outputted, that is, the output signal out outputted from the output terminal of the shift register is shifted by half of a clock cycle with respect to the input signal in.
However, in driving the shift register, the output terminal OUT shall be at a stage of maintaining a high level after outputting the low level signal, the level of a node N2 can be pulled down somewhat in the case where a level of the second clock signal ckb is changed from a high level to a low level, and hence the output terminal is affected due to the coupling effect of the second capacitor C2, that is, the output signal is unstable and severely distorted. The distortion of the output signal will affect the operation reliability of the gate driver, and hence affect the quality of the image displayed by the Liquid Crystal Display.
Therefore, there is an object of the present invention to provide a shift register which outputs a signal with minimal or no distortion.